May 5, 2015
Review session notes (handwritten):
Tues., 5 May
In-class notes (handwritten):
micro 7, xmsssn lines, projects, Thu. 30 April
(handwritten): micro 6, peripherals, big quiz, Tues. 28 April
April 27, 2015
HW D6, due Monday, May 4
8051 template file, react_time_MT_apr15.a51
for HWD5 (open with Ride or Wordpad)
In-class notes (handwritten): micro 5, tables, Thu. 23 April
Apr. 23, 2015
Note that your "path" that tells the assembler/compiler where to find files, which is "$INCLUDE (C:\MICRO\8051\RAISON\INC\c8051f410.inc)",
for example, in one of our .a51 source files, may differ on a particular computer which has stored it elsewhere. We've tried to place these files
in the same paths on the lab machines, but may have failed on a particular machine.
Sampleprograms (some of those used in the SiLabs micro labs)
Sampleprograms (some of those used in the 'Big Board' Dallas micro labs)
Apr. 22, 2015
Class notes (handwritten) micro 4, interrupt, Tues., 21 April
April 20, 2015
HW D5, due Monday, April 27
Verilog template file, reaction_timer_april2011_MT.v, for HWD5
Note that you ought to remove
the "MT" from the file when it is no longer empty, so as to make it fit the testbench. Probably this point is familiar to you, by nyw.
Verilog testbench file, reaction_timer_april2011_tb.v, for HWD5
Note that this testbench
name does not include the "MT."
Class notes (handwritten) micro 3, subroutine CALL, Thu.., 16 April
Apr. 15, 2015
Class notes (handwritten) micro 2, i/o, Tues., 14 April
Raison 8051 assembler and simulator
Here is the excellent free program (free for code size under 8K) that I use to assemble and simulate code.
Link to Raisonance site Here you need
to register (as for Xilinx), then can download RIDE7, a sort of framework, along with RKIT-51, the tool for 8051
assembly, simulation and C compiling. RIDE is not huge on the scale of Xilinx ISE.
If you'd like to bypass the registration and loading of two programs, here is an older version of RIDE, one that I think will
run satisfactorily. It's not the version I now use: kit51_747_.exe: zipped Raisonance assembler,
compiler & simulator. (18.5M, expands to 50M)
References for Raisonance RIDE assembler/C-compiler/simulator
And here--long before you'll need it--is a file of vector names--an".INC" file that zealots
will want to include in the INC directory oftheir Raisonance/Ride installation! (I realize I may be speaking to no one atall.)
Here it is: a table of symbolic names
for the80C320's vector addresses
(for use with a program that relies oninterrupts). These vector addresses are
the same for the DS89C420 and DS89C430, incidentally.
Link to RIDE documentation: detailed user's guide
I expect this is much more than you want; but here it is, anyway, for thezealot
who wants the full story about the Raisonance assembler, compiler &simulator.
It's a zipped file (about 37M),and includes instructions.
When we ask you to do some coding, Ride will help a lot, though
it is notessential (you can use the programmer's reference, in the posted set ofsources, to see the instruction set. You may not
need even that: some preferjust steal code from the lab programs!).
ShortNote on how to use the RIDE Assembler & Simulator
Apr. 13, 2015
HW D4, due Monday, April 20
Labs: Big Board
Lab micro1: Big Board (Dallas branch)
Lab micro2: Big Board (Dallas branch)
Lab micro 3: Big Board (Dallas branch)
Lab micro 4: Big Board : ADC (Dallas branch)
Lab C1: startup (SiLabs branch)
Lab C2: byte in, out (SiLabs branch)
Lab C3: timers (SiLabs branch)
Lab C4: ADC, DAC (SiLabs branch)
Apr. 11, 2015
In-class notes (handwritten): micro 1, Thu. 9 April
Apr. 7, 2015
Class notes (handwritten) project day, fragments;
Apr. 6, 2015
HW D3, due Monday, April 13
Verilog template file, hw_adr_decode_MT.v, for HWD3
(not required; you can
do the problem with pencil and paper)
Verilog template file, two_bit_simplest_ctr.v, for HWD3
Verilog testbench file, three_bit_sync_clear_tb.v, for HWD3
Apr. 2, 2015
Class notes (handwritten) digital 5, ADC, Thu., 2 April
Bidirectional logic-level signal translator, by Philips
Just for fun. An ingenious use of a single transitstor.
Mar. 31, 2015
Class notes (handwritten) digital 4, memory, Tues., 31 March
Class notes (handwritten) digital 3, counters, Thu., 26 March
March 30, 2015
HW D2, due Monday, April 6
Lab 18p: digital project lab
Verilog template file, stepglue_MT_nov12.v, for HWD2
Verilog testbench file, stepglue_MT_nov12_tb.v
A Logic Compiler
Verilog download, free from a PLD manufacturer, Xilinx. The download is very large. You'll find the program here:
Xilinx Verilog download
(restricted to Xilinx parts)
; download ISE, NOT VORNADO.
Click on ISE (you'll get the free Weback), register, and download version 14.7, the most recent (and last , any sub-revision. You do not need the ModelSim simulator, and when you create a project should choose
the ISE simulator, not the Modelsim simulator.
Note on Xilinx ISE, more generally: Verilog and ABEL
Mar. 25, 2015
Class notes (handwritten) digital 2, Tues., 24 March
March 23, 2015
HW D1, due Monday, Mar. 30
17S2 note on Address Decoding
Possibly helpful on HW D1
Mar. 13, 2015
Class notes (handwritten) digital 1, Thurs., 12 March
Lab 15: digital 2, flip-flops
Class 15 notes (typed): Digital 2
(page one is blank)
Mar. 10, 2015
Analog review notes (typed, from Dec. 2013)
A solution, like yours, to group audio design task
Mar. 8, 2015
In-class notes (handwritten): midterm review session, Sun. 8 Mar..
Mar. 6, 2015
In-class notes (handwritten): MOSFETs, Thu. 5 Mar..
Mar. 4, 2015
In-class notes (handwritten): voltage regulators, Tues. 3 Mar..
In-class notes (handwritten): nasty oscillators, Tues., 24 Feb.
Feb. 27, 2015
In-class notes (handwritten): PID, Thu., 26 Feb.
Feb. 23, 2015
HW 4, due Monday., Mar. 2
Lab 10: Op-amps V, PID motor control loop
Feb. 20, 2015
In-class notes (handwritten): oscillators, Thu., 19 Feb.
HW 3, due Monday., Feb. 23
Feb. 18, 2015
In-class notes (handwritten): op amps II, Tues., 17 Feb.
Lab 9: Op-amps IV, nasty pos feedback
Feb. 16, 2015
In-class notes (handwritten): op amps I, Wed.,Fri., 11, 13 Feb.
In-class notes (handwritten): transistors 2, Thu., 12 Feb.
Feb. 11, 2015
Class 6 notes (typed): Op Amps I
HW 2, due TUESDAY., Feb. 17, AT CLASS
Lab 6: Op-amps I
Lab 7: Op-amps II, imperfect op-amps
Lab 8: Op-amps III, oscillators
Feb. 6, 2015
In-class notes (handwritten): transistors I, Thu.., 5 Feb.
Lab 5: Transistors II (bipolar)s
Feb. 4, 2015
In-class notes (handwritten): diode Circuits, Tues., 3 Feb.
Feb. 2, 2015
HW 1, due Mon., Feb. 9
Lab 4: Transistors I (bipolar)s
January 30, 2015
First in-class notes (handwritten): RC Circuits, Jan. 29
Lab 3: Diode Circuits
Blizzard Update: January 26, 2015
As I'm sure you've heard, Harvard is closed on what would have been our first class day, Tuesday, Jan. 27.
We'll essentially abandon that class day. It includes just one important notion that may be new to you: Thevenin's Theorem or his "model"
of resistive circuits. We will talk of Thevenin on Thursday (Jan. 29) and then will hurry on into the more interesting (and challenging) material of Day 2.
Here are the typed classnotes for Day2. Please look through these, and leaf through Lab 2 so you'll know what's coming.
Class 2 notes: RC's (typed)
Spring INFORMATION: January 12, 2015
Course Information: intro and schedule
We will hold a normal class and lab on the very first day, Tues., Jan. 27: Please read class and lab notes for Day 1 before you come in.
The course meets in Science Center 206
1st-day Signup Form
Class 1 notes (typed): DC Circuits
Lab 1: DC Circuits
Lab 2: RC Circuits
Hints and Tips, illustrated
An excellent introduction to lab setups, by Summer School and SEAS instructor David Abrams
Link to Text problem solutions, and old exams (some with solutions)
Click here to hop to old Finals, and Text-problem solutions
Files are in Acrobat (PDF) Format, Download Acrobat Reader
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