Tom's Physics 123 Page

May 9, 2013

Review session notes (handwritten): 8 May, 2013
Review notes (typed)
correction for page 3 of supp note 17S2 (re address decoding))
HWD6 solution
HWD2 solution I think I never distributed this one. Sorry it's late.

May 1, 2013

Paul Horowitz' transmission line talk, Tues., 31 April, 2013
Class mu5 notes (handwritten): tables, serial protocols, Thurs., 25 April, 2013

April 29, 2013

HWD6, due Monday, May 6, 2013 This is a tiny, toy homework. We know that exam time is getting uncomfortably near. Mostly it's a reminder of moving-pointer use.

April 15, 2013

HWD4, due Monday, April 22, 2013
reaction_timer_april2011_MT.v template file (design)
reaction_timer_april2011_tb.v template file (testbench)
reaction_timer_april2011.ucf reaction_timer_april2011.ucf: signal placing file; this you won't need till you want to burn the par.

April 13, 2013

Class mu1 notes (handwritten):, Thurs., 11 April.\, 2013
Class 18a/D6 notes (handwritten): project fragments, Tues., 9 April.\, 2013
Typed Classnotes for Micro 2
Lab mu2: big board: I/O
Lab Controller 2: SiLabs
Note on Addressing Modes: bit, byte

Here's a large block of reference materials, re 8051 in its two versions, and the RIDE assembler & simulator

We don't expect you to read through this great blob of stuff. It's here for occasional reference.

8051 References

8051Instruction Set Reference (Phillips) We will give you this in xeroxed form, as well.
8051 tutorial,from Web

Interrupt Vectors File (for both SiLabs and Dallas)

".inc" file listing addresses of interrupt vectors This file, vectors320.inc, is "included" in many of the templates and sample programs that we have posted. It tells the assembler where to place the interrupt response routines. It allows you to write "int0vector" and have the assembler look up what that address is (03h, it turns out).

Data sheets and info for the two versions of the 8051

Data sheet for SiLabs C8051F410 controller
Data sheet for Dallas DS89C420/30 controller, used in 'Big Board' version of labs
Dallas high speed microcontroller User's Guide
Index to selected topics in Dallas User's guide

Raison 8051 assembler and simulator

Here is the excellent free program (free for code size under4K) that I use to assemble and simulate code. kit51_747_.exe: zipped Raisonance assembler, compiler & simulator. (18.5M, expands to 50M)

References for Raisonance RIDE assembler/C-compiler/simulator

And here--long before you'll need it--is a file of vector names--an".INC" file that zealots will want to include in the INC directory oftheir Raisonance/Ride installation! (I realize I may be speaking to no one atall.) Here it is: a table of symbolic names for the80C320's vector addresses (for use with a program that relies oninterrupts). These vector addresses are the same for the DS89C420 and DS89C430, incidentally.

Link to RIDE documentation: detailed user's guide

I expect this is much more than you want; but here it is, anyway, for thezealot who wants the full story about the Raisonance assembler, compiler &simulator.
Part I
Part II

It's a zipped file (about 37M),and includes instructions.
When we ask you to do some coding, Ride will help a lot, though it is notessential (you can use the programmer's reference, in the posted set ofsources, to see the instruction set. You may not need even that: some preferjust steal code from the lab programs!). The file: ShortNote on how to use the RIDE Assembler & Simulator

Sample Programs

SiLabs Programs

Sampleprograms (some of those used in the SiLabs micro labs)

Dallas Programs

Sampleprograms (some of those used in the 'Big Board' Dallas micro labs)

April 10, 2013

Typed Classnotes for Micro 1
Lab mu1: big board
Lab Controller 1: SiLabs

April 8, 2013

HWD3, due Monday, April 15, 2013
two_bit_simplest_ctr.vtemplate file (design)
three_bit_sync_clear_tb.vtemplate file (testbench)

Verilog testbench file, stepglue_MT_nov12_tb.v Typo corrected 4/8/13
The testbench posted included a deadly typo: ``steplue_MT_nov12 uut". Profuse apologies! Posted testbench is corrected.
Class 18/D5 notes (handwritten): analog<-->digital, Thurs., 4 April, 2013

April 4, 2013

A Logic Compiler

Verilog download, free from a PLD manufacturer, Xilinx. The download is very large. You'll find the program here: Xilinx Verilog download (restricted to Xilinx parts); Click on ISE WebPACK, register, and download version 14, any sub-revision. You do not need the ModelSim simulator, and when you create a project should choose the ISE simulator, not the Modelsim simulator.

April 3, 2013

Class D4 notes (handwritten): counter application, state machines, Tues., 2 April, 2013
Lab 18/D5: Analog<-> Digital
Class notes 18/D5 (typed) : Analog<-> Digital

April 1, 2013

HWD2, due Monday, April 8, 2013
Verilog template file, stepglue_MT_nov12.v
Verilog testbench file, stepglue_MT_nov12_tb.v Typo corrected 4/8/13

Mar. 31, 2013

Typed class notes 17, D4: memory
Lab D4: Memory, State Machines
Note on Digital Debugging
Note on Address Decoding

Mar. 30, 2013

Class 16/D3 notes (handwritten): Counters, Thurs., 28 Mar., 2013
Class 15/D2 notes (handwritten): Flip-Flops, Tues., 26 Mar., 2013

Mar. 25, 2013

HWD1, due Monday, April 1, 2013

Mar. 16, 2013

Class 14/D1 notes (handwritten): Gates, Thurs., 14 Mar., 2013

Mar. 11, 2013

Midterm review session notes (handwritten), Sunday, 10 Mar., 2013

Mar. 8, 2013

Midterm details: The midterm test will be held, as you know, Wed., Mar. 13, 8 to 9:15 pm. You did not know the room, but we now have one: Jefferson 256. If you know where my office is, finding 256 is easy: pass my office, room is the next door on the right. If you don't know Jefferson, it's the big old brick building of 4 storeys, about 100 yards north of the Science Center. Use the westernmost entrance. At the test, you're invited to bring a calculator (of course) and also a one-sided letter-size `cheat sheet' with your handwritten notes. On Sunday (Mar. 10) in place of the usual free office hours we'll do a raggedy review (Tom) 4 to 5, then Tom and one of our faithful TA's will hang around for one-on-one questions. During the days that follow, last-minute questions are welcome. I'm usually in my office most of the day: roughly 9:30 to 6. If it's not convenient to come to Sunday's review gathering, don't worry: nothing surprising will emerge. I usually ask the group to nominate topics, and then I try to find some themes to unite the discussion of these. I'll post whatever notes the session produces.
Class 12 notes (handwritten): MOSFET's, Thurs., 7 Mar., 2013
Class 11 notes (handwritten): voltage regulators, Tues., Mar. 5, 2013
Lab 12: group audio project
Lab 11: MOSFET's